This invention relates to synchronous data detection, and more specifically, relates to a phase detection circuit that operates in multiple capacities of synchronous data detection.
In systems for synchronous transmission of digital data, an information signal is sent from a transmitting unit to a receiving unit. This transmission may take place over serial or parallel data channels. In either case the data is sent in synchronism with a clock signal. In order to save bandwidth, the clock signal is normally not transmitted with the data. Hence, the receiving unit receives the signal at the same clock rate at which it is transmitted.
Two typical methods for transmitting digital data are baseband and carrier-based transmission. In baseband transmission, a signal is sent directly over a communications link. In carrier-based transmission, the signal is first modulated onto a carrier signal. The modulated carrier signal is then sent to the receiving unit. Common modulation techniques include amplitude modulation (AM), frequency modulation (FM) and phase modulation (PM). When a modulated signal reaches the receiving unit, it is demodulated from the carrier signal to its original form by demodulation circuitry.
The receiving unit then extracts the clock from the baseband or demodulated carrier-based signal in order to generate a reference by which the data can be interpreted. The method for extracting the clock depends on the type of data format used in the binary signal. Some examples of data formats are non-return to zero (NRZ), return to zero (RZ), biphase and delay-modulation.
Each format has associated advantages and disadvantages. The RZ format, for instance, contains a spectral line at the clock frequency, which makes clock recovery easy. The NRZ format, conversely, does not necessarily contain a spectral line at the clock frequency and requires additional circuitry for extraction. The NRZ format is advantageous in another way, however, in that it uses half the bandwidth as does the RZ format, which increases the amount of data that can be sent. Hence, data formats are chosen primarily by the needs and allowances of the particular application.
When using a format such as the NRZ format, the clock must be recovered from the signal. This operation is typically performed by a phase-locked loop (PLL). As depicted in FIG. 1, a PLL 100 typically comprises phase offset detection circuitry 102, loop filter circuitry 104 and a voltage controlled oscillator (VCO). PLL 100 modulates VCO 106 until it is in phase with the incoming data. The signal generated by VCO 106 is then used as the reference clock to interpret the data signal.
In order to do this, phase detector circuit 102 detects the phase difference between the incoming data signal and the output of VCO 106 and generates phase detection signals 108. Phase detection signals 108 have a difference in average value that corresponds to the difference in phase between the incoming data signal and the VCO 106 output. Loop filter 104 converts the difference in average value into an analog voltage signal and filters the signal to remove extraneous noise. An example analog voltage signal 200 is shown in FIG. 2A. Signal 200 is fed to VCO 106, which slows down or speeds up in response, bringing the output of VCO 106 into phase with the incoming data. Once aligned with the incoming data, the output of VCO 106 is used as the clock signal for interpreting incoming data
A conventional PLL circuit 300 containing a phase detector 330 is depicted in FIG. 3. A description and operating theory behind circuit 300 can be found in xe2x80x9cA Self Correcting Clock Recovery Circuit,xe2x80x9d IEEE Journal of Lightwave Technology, vol. LT-3, pp. 1312-1314, Dec. 1985. Circuit 300 provides a basic means for aligning data and clock phase and comprises phase detector 330, loop filter 328 and VCO 314.
Phase detector 330 comprises two D flip flops 302 and 304 connected in series, and two XOR gates 306 and 308 tied to the input and output of, respectively, flip-flops 302 and 304. Incoming data is supplied to input node 310 of flip-flop 302 and the input of XOR gate 306. VCO 314 provides a clock signal to flip-flop 302 at its clock input node 316. D flip-flop 302 enables its output 312 on every rising edge of this clock signal. Output 312 is connected directly to the input of XOR gates 306 and 308, as well as to the input to D flip-flop 304. D flip-flop 304 enables its output 318 on the rising edge of the inverted clock signal provided by VCO 314. Hence, flip-flops 302 and 304 operate one-half clock cycle apart. The output 318 of D flip-flop 304 is connected to the second input of XOR gate 308.
Phase detector 330 produces two phase detection signals by which the phase offset is measured. The phase detection signals, commonly referred to as reference signals, are square pulse signals generated for each transition of the incoming data and having a fixed width equal to half the clock period. The first phase detection signal is output 324 of XOR gate 308. It is a square pulse signal commonly referred to as a reference signal that is generated for every transition of the incoming data and has a fixed width equal to half the clock period.
The second phase detection signal is provided by the output 322 of XOR gate 306. The second phase detection signal is a variable width, square pulse signal with a pulse generated for every transition of the incoming data. The width of this square pulse is dependent upon the position of the rising clock edge in relation to each incoming data transition. This signal is commonly referred to as an error signal. When the rising edge of the clock is in phase with the incoming data, the width of the data pulses produced in the error and reference signals are the same. There is no difference in average value between the signals and correspondingly, the frequency of VCO 314 is not modulated.
When the rising edge of the clock lags behind the incoming data transition, the data pulse in the error signal decreases in width and has an average value less than the fixed width pulse of the reference signal. As a result, a negative error voltage is produced by loop filter 328 and fed to VCO 314. When the rising edge of the clock arrives before the incoming data transition, the data pulse in the error signal increases in width and has an average value more than the fixed width pulse of the reference signal. As a result, a positive error voltage is produced by loop filter 328 and fed to VCO 314.
As data frequencies rise, the delay, hold and setup times associated with circuit 300 become smaller in order to accommodate shorter data pulse widths and to guard against timing violations. However, phase detector 300 will begin to experience difficulty at these higher frequencies. Properly balancing propagation delays and drive strengths of the D flip-flops 302 and 304 becomes very difficult. In order for the flip-flops to be powerful enough to drive their outputs to satisfy shorter hold and setup times, they must be larger in terms of circuit geometry. But as their size increases, the distance the distance that data signal 310 must travel also increases and creates longer propagation delays. The propagation delays will begin to violate the hold and setup times of the various logic gates and the circuit will fail to recognize data pulses. These pulses are generally referred to as xe2x80x9cmissed pulses.xe2x80x9d Missed pulses can translate into a xe2x80x9cdead zonexe2x80x9d in the analog voltage signal at the phase detector output, resulting in phase jitter. An analog voltage signal 202 with a dead zone 204 is demonstrated in FIG. 2B.
Phase jitter is a time variation in the clock edge produced by VCO 106, in which the edge moves back and forth instantaneously and oscillates around the targeted position. This is undesirable because it results in a dynamically varying amount of time available for logic computations. Phase jitter translates to phase noise in the frequency domain, and can prevent PLL 100 from locking on the correct data frequency. This is a serious problem because it prevent the receiving unit from correctly reading the transmitted data.
The present invention provides an improved error and reference signal generation method in the phase detection circuitry. This improvement permits high frequency signal phase alignment when incorporated into a phase-locked loop. The improvement also facilitates the balancing of flip-flop size, strength, and density, while maintaining a low propensity for phase jitter at higher frequencies. The improved phase detector system may be broadly conceptualized as a system that uses multiple sections and cascades them in order to prevent timing errors such as missed pulses. This allows the system to operate at higher frequencies without the addition of large amounts of complex circuitry and without the need for highly tuned fabrication processes.
A phase locked loop that implements an improved phase detector circuit in accordance with the present invention comprises a first section configured to generate a first output signal from an input signal on a first clock edge. The first section also generates a second output signal from the input signal on a second clock edge.
The first section is coupled to a second section configured to generate a third output signal from the first output signal on the first clock edge. The second section also generates a fourth output signal from the second output signal on the second clock edge. By generating the third and fourth output signals on the same clock edge as used in the first section, as opposed to the opposite clock edge, the circuit effectively doubles the time available for correct signal interpretation. This allows for operation at higher frequencies.
The input signal and the first output signal can also be coupled to a third section, which is configured to compare the two signals and to generate a first phase detection signal based on the comparison. The first phase detection signal comprises a pulse for every input signal pulse. The width of the first phase detection signal pulse is dependent on the phase difference between the clock signal and the input signal.
The outputs of the first section and the second section can be coupled to a fourth section, configured to compare the two signals and to generate a second phase detection signal based on the comparison. The second phase detection signal comprises a pulse for every input signal pulse. The width of the second phase detection signal pulse is independent of the phase difference between the clock signal and the input signal, and is used as a reference signal.
Comparison of the average values of the two phase detection signals provides a method for detecting phase offset between the input signal and the clock signal. This information can be fed to a clock generator that can increase or decrease its frequency to bring the input signal and clock signal into phase.
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.